Theory of Operation
This document explains the way Durango-X is designed. Since one of its goals is the use of standard 74xx logic circuits, the schematic may appear pretty complex at first sight, but it's easily understood with the help of this guide.
This is also a good complement to the Troubleshooting guide.
Block Diagram
Unlike many Single Board retro-Computers, Durango-X's main feature is the built-in video output. This is achieved by multiplexing the RAM's address bus between the CPU and the video address generation circuit, for optimum performance -- no wait states nor snow during screen accesses!
Here's a simplified Block Diagram showing Durango-X's major blocks and most of its interconnections:
Circuit description
Note
Details on this description apply to Durango-X revision v1. Changes included in the new v2 revision will be noted; otherwise, it's all the same.
According to a modular approach as suggested by EmilioLB, several big blocks can be isolated:
- Clocks: generation of both video and CPU clock signals, as they're fully synchronised for optimum performance.
- VDU: picks video data from SRAM and sends it to the monitor thru some analogue circuitry.
- SCART: the actual analogue circutry for sending the video output.
- CPU: the brains of the machine.
- MUX: the RAM needs to be multiplexed between the CPU and the video circuitry.
- Base I/O: basic on-board devices.
- Extra features: not indispensable, but useful anyway.
- Interface: external devices and connections.
Clocks
For optimum performance, the 24.576 MHz master clock X1 is used to generate both video addresses and system clock, in perfect sync -- the later originally called SCLK but shown in most schematics as VCLK, since it's the same for both parts. Both sections run at 1.536 MHz, from a divide-by-16 prescaler included into U15 (74HC4040), then inverted via U16 (74HC02) for adequate phase against other high frequency signals (mainly used for the HIRES video mode).
SCLK is further divided thru the remaining stages of U15, together with the AND gate U17 (74HC21) configured as a divide-by-98 counter reset by the LEND signal. Thus, the horizontal sync frequency is generated, albeit at a slightly non-standard 15673 Hz, which is near enough to the CCIR standard 15625 Hz. From these 98 clock cycles, the first 64 cycles define the active region of each scanline as the /LINE signal (directly from U15's Q9 output). This signal get used as the clock signal of the line counter U19 (another 74HC4040).
A proper horizontal sync pulse must be generated within the inactive 34 clock cycles. This pulse has a width of 8 clock cycles or ~5.2 µs, pretty close to the specified 4.7 µs, easily achieved by using the VA3-VA6 outputs from U15 into a 4-bit magnitude comparator U18 (74HC85) aginst a fixed number 9, so the sync pulse (UHS, active-high) will be sent while the count values are between 72 and 79, as 9 x 8 = 72. This results in a slightly off-centre image to the right, but good enough for most (if not all) monitors.
A minor drawback of this simple approach is the inversion of the horizontal pulse during the vertical sync, as both signals get combined into CSYNC thru an EXOR gate U23 (74HC86), which may cause some instability for some displays. Since most TVs do actually sync on the high-to-low sync flange, the remedy for this is quite simple: during vertical sync, generate the UHS pulse earlier by 8 clock cycles (count 64 to 71), simply by aplying the inverted /VS signal to the U18 comparator, in order to compare the aforementioned video address bits against 8 during this stage.
Note
Revision v2 uses a 28 MHz main oscillator which, after the prescaler and a divide-by-112 horizontal counter, gets the CCIR-specified 15625 Hz horizontal frequency. For better centering, horizontal sync is generated at clock count 88 instead of 72.
VDU
SCART
CPU
MUX
Base I/O
Extra features
Interface
