Theory of Operation
This document explains the way Durango-X is designed. Since one of its goals is the use of standard 74xx logic circuits, the schematic may appear pretty complex at first sight, but it's easily understood with the help of this guide.
This is also a good complement to the Troubleshooting guide.
Block Diagram
Unlike many Single Board retro-Computers, Durango-X's main feature is the built-in video output. This is achieved by multiplexing the RAM's address bus between the CPU and the video address generation circuit, for optimum performance -- no wait states nor snow during screen accesses!
Here's a simplified Block Diagram showing Durango-X's major blocks and most of its interconnections:
Circuit description
Note
Details on this description apply to Durango-X revision v1. Changes included in the new v2 revision will be noted; otherwise, it's all the same.
According to a modular approach as suggested by EmilioLB, several big blocks can be isolated:
- Clocks: generation of both video and CPU clock signals, as they're fully synchronised for optimum performance.
- VDU: picks video data from SRAM and sends it to the monitor thru some analogue circuitry.
- SCART: the actual analogue circutry for sending the video output.
- CPU: the brains of the machine. Includes interrupt generation.
- MUX: the RAM needs to be multiplexed between the CPU and the video circuitry.
- Base I/O: basic on-board devices.
- Extra features: not indispensable, but useful anyway.
- Interface: external devices and connections.
Clocks
For optimum performance, the 24.576 MHz master clock X1 is used to generate both video addresses and system clock, in perfect sync -- the later originally called SCLK but shown in most schematics as VCLK, since it's the same for both parts. Both sections run at 1.536 MHz, from a divide-by-16 prescaler included into U15 (74HC4040), then inverted via U16 (74HC02) for adequate phase against other high frequency signals (mainly used for the HIRES video mode).
SCLK is further divided thru the remaining stages of U15, together with the AND gate U17 (74HC21) configured as a divide-by-98 counter reset by the LEND signal. Thus, the horizontal sync frequency is generated, albeit at a slightly non-standard 15673 Hz, which is near enough to the CCIR standard 15625 Hz. From these 98 clock cycles, the first 64 cycles define the active region of each scanline as the /LINE signal (directly from U15's Q10 output), when the remaining U15's Q4 to Q9 outputs act as the video address lines VA0 to VA5. That /LINE signal is used as the clock signal of the line counter U19 (another 74HC4040).
About the aforementioned line counter, since a proper computer TV display output must be non-interlaced, U19 together with the other AND gate in U17 is configured as a divide-by-312 counter, which leads to a slight vertical frequency increase, as was common in most home computers. This counter emits the remaining video address lines VA6 to VA13 from its Q0 to Q7 outputs. Accordingly, Q8 generates the /FRAME signal in a similar way to /LINE, thus marking the 256 active rasters period.
Note
Not all video address lines are used simultaneously. Depending on the active video mode, the needed 74HC257 multiplexers are enabled (either U104/U105 or U204/U205), plus the common-to-all-modes U6 and U7 (74HC157).
A proper horizontal sync pulse must be generated within the 34 inactive clock cycles per raster. This pulse has a width of 8 clock cycles or ~5.2 µs, pretty close to the specified 4.7 µs, easily achieved by using the Q7-Q10 outputs from U15 into a 4-bit magnitude comparator U18 (74HC85) aginst a fixed number 9, so the sync pulse (UHS, active-high) will be sent while the count values are between 72 and 79, as 9 x 8 = 72. This results in a slightly off-centre image to the right, but good enough for most (if not all) monitors.
A minor drawback of this simple approach is the inversion of the horizontal pulse during the vertical sync, as both signals get combined into CSYNC thru an EXOR gate U23 (74HC86), which may cause some instability for some displays. Since most TVs do actually sync on the high-to-low sync flange, the remedy for this is quite simple: during vertical sync, generate the UHS pulse 8 clock cycles earlier (count 64 to 71), simply by applying the inverted /VS signal to the U18 comparator, in order to check whether the aforementioned video address bits stay at 8 during this stage.
About the vertical sync pulse, it is generated in a similar way within the 56 inactive rasters. This pulse has a width of 4 rasters or ~256 µs, acceptably close to the specified 160 µs, once again achieved by using the Q2-Q5 outputs from U19 into another 4-bit magnitude comparator U20 (74HC85) aginst a fixed number 8, but only enabled while /FRAME is high (blanking period), so the sync pulse (UVS, active-high) will be sent when the raster count is between 288 and 291, as (8 x 4)+256 = 288. Vertical centering is usually OK, although the 256 active raster area may be a tight fit for some monitors.
Note
Revision v2 uses a 28 MHz main oscillator which, after the prescaler and a divide-by-112 horizontal counter, gets the CCIR-specified 15625 Hz horizontal frequency. For better centering, horizontal sync is generated at clock count 88 instead of 72. No changes are made for the vertical counter.
60 Hz EIA (NTSC) version
This is under development as a derivative from v2. It's intended to use a readily available 25.175 MHz oscillator and a divide-by-100 horizontal counter for a nominal 15734 Hz horizontal rate. The line counter is based on a divide-by-262 counter but, since there's no way to display 256 rasters on an EIA/NTSC screen, the \FRAME signal needs an extra IC (74HC85) in order to make just 192 active rasters.
Overclocking Durango-X
Although the v2 revision will include a TURBO setting option, it is possible to overclock an existing v1 Durango-X with some mods, while keeping the proper sync frequencies for a working display. This involves some trace cutting, bodge wiring and even adding some extra circuitry. Check this other page for more information on the several overclocking methods available.
Warning
Since the video clocks (and thus, the sync frequencies) are derived from the master clock, trying to overclock Durango by merely changing the main oscillator frequency will result in a non-functional video output -- in extreme cases, the display itself might be damaged!
VDU
While the 65C02 CPU has full access to RAM during the Phi2 clock phase (SCLK high), the Phi1 phase (SCLK low) grants RAM access to video circuitry. Display data in RAM is read then according to the current VAx video address lines, at full clock rate in colour mode but half the speed (768 kHz) in HIRES. Thus, no video noise or performance penalty is made during CPU accesses to display data.
Depending on the current video mode, this display data follows different paths. In HIRES, data is latched by the U224 shift register (74HC166) at the precise moment determined by U227A (/PE signal) combining some of U15's highest bits. This data is shifted out at a 6.144 MHz dot clock rate (HDOT). This serial output (HPIX) may be inverted thru an XOR gate (U23C, 74HC86) for the actual pixel stream to be displayed (HVID). This signal might suffer a small delay from RV231 for timing calibration, turning into DHVD which is gated thru U227B (74HC20) as requested during blanking periods by the DHRDE signal. Being a NAND gate, this inverted signal (/HVG) goes back to normal thru another XOR gate (U23D) configured as a fixed inverter, where the definitive video stream HVG is obtained.
Note
Dot clock on the v2 issue is 7 MHz (the 1.75 MHz SCLK frequency times 4), allowing the display of perfectly square pixels with an 1:1 aspect ratio.
Note
Pull-up and pull-down resistors are used in a few U23 inputs, just in case U227 is not installed (colour-only Durango-S option). These are not needed otherwise, but won't hurn anyway.
On the other hand, video data path in colour mode is somewhat less convoluted. Display data is latched via U124 (74HC574) at VCLK rate. We're dealing with chunky 4 bits per pixel, thus every byte contains two pixels which must be serialized at the same rate via the U125 (74HC157) multiplexer, which has a slightly faster propagation time than the former IC. For optimum picture quality, RV127 creates a slight delay (DEV/ODD) which may adjust the Pixel Delay between both nibbles. Finally, this 4 bpp stream (XB, XR, XGL and XGH) goes thru a dedicated XOR inverter (U126, 74HC86) in case the Inverse video mode is enabled, creating the desired pixel stream lines (IB for blue, IR for red, IGL and IGH for green). This stream is not gated as that will be done on the SCART section.
SCART
This circuit creates the analog video signals from the digital streams provided by the VDU section, no matter the connector used. The main circuit is made around Q4 and Q5 transistors (BC548). Q4is configured as a common-base mixer for high bandwidth and negligible signal interaction, taking the composite sync /CSYNC signal and mixing it with the HIRES video stream HVG at appropriate levels (actually around 2 Vpp as common practice). This ZMIX signal is then buffered via Q5 as an emitter follower for low impedance output (MIX). A 75 ohm series resistor (68 is acceptable too) provides short circuit protection and gets the signal down to the standard 1 Vpp level and impedance. Actually, two of these outputs are provided, for both SCART (R30/C5) and RCA (R31/C9) sockets.
Tip
Q5 buffer uses a bias resistor (R15) whose 330 ohm is determined for the use of either SCART or RCA output, but not simultaneously. In case both outputs are needed at the same time, R15 must be reduced accordingly (say, to 150 ohm) for safe operation. This lower value will work in any case, at the expense of somewhat increased power consumption.
In colour mode, the above circuit is mainly used for sync signals. The SCART connector provides RGB inputs when switched via the fast blanking input. The colour bitstreams coming from VDU (IB, IR, IGL, IGH) are buffered by U127 (74HC245) which in turn disables video output during blanking periods from the /DCDE signal. Together with the previous DHRDE, these signals come from /CDE and HRDE generated at U3xx (74HC175) after some adjustable delay via VR128 and VR221, respectively. The buffers in the '245 are used in pairs for minimal output impedance, and the outputs go into two separate paths: main one is a simple DAC for each colour in order to attenuate the signals down to the nominal 0.7 Vpp expected by each RGB input's 75 ohm standard impedance -- in case of the green channel, two bits are in use, which account for approx. 1/3rd and 2/3rds of the full-scale output, rendering three levels of green plus black.
The remaining path is sort of an afterthought... In case the RGB mode is not supported (or the SCART connection is missing altogether), an approximate luminance value is supplied to the composite output. A crude DAC is made upon R107...R110 which apply a suitable current level to the common ground input VIN of the aforementioned video mixer, so at least a monochromatic image is displayed.
Tip
The DAC resistor values stated in the silkscreen (v1 issue) are intended for a reasonably linear greyscale, which may be enabled by clearing bit D3 of the video mode register ($DF80, not officially supported). But since this mode seems of little use, and might render somewhat inaccurate colours if the RGB-to-component video converter is used, alternative values may be used. Check the Palette article for details.
v2 and later issues of Durango-X include the luminance DAC as standard.
The way for switching the TV between the composite and RGB inputs is via the fast blanking input in the SCART connector. This receives the RGB signal from U3xx (which is either 0 in HIRES mode, or the value of D3 from the video mode register), buffered by Q306 and applied thru R312.
Note
The fast blanking signal does draw a lot of current, accounting for nearly one third (!) of Durango-X's total power consumption. Increasing the value of R312 to suit your particular TV will decrease energy usage, but might be the cause of unreliable mode switching.
This resistor is not used in Composite, Sync-on-Green or (for v2 and later) Component video outputs, thus greyscale mode is not available.
CPU
The CPU section on the Durango-X computer is based around the 65C02 microprocessor U1 and its associated circuitry -- mainly, interrupt generation. Please note that the Durango-X board has no ROM at all, relying on the one on the cartridge, which is essential for operation. RAM is also surrounded by the multiplexing circuitry described below.
U9 (74HC00) generates the bare minimum control signals, according to these equations:
ROM /CSisA15NAND/IO, thus ROM will be disabled while accessing the I/O area ($DF80-$DFFF)ROM /OEcomes thru the NAND fromR/W, but also gated viaSCLK, as ROM must leave the data bus free during _Phi1 phase (while video data is collected by the VDU)/WEis generated the usual way, gating withSCLKthe aforementionedROM /OEsignal, even if it's already SCLK-gated, as is a conveniently invertedR/W. This signal is sent to the corresponding pin on the cartridge slot but is not directly used by the RAM, as being multiplexed calls for an additional delay for the address lines to settle.
The remaining gate is used to invert the HIRES signal for selecting the adequate bank of multiplexers.
Note
In the v2 issue, this spare gate has a different purpose, creating the 3.5 MHz clock signal for the TURBO option, whereas the HIRES signal is inverted thru a transistor Q307.
Interrupt generation
The IRQ-generating circuit in Durango-X is designed around the minimOS standard 250 Hz periodic interrupt (4 ms period). For accurate timing, the VA0 signal (768 kHz) is further divided by 3072 thanks to U14 (74HC4040) and one NAND gate from U8 (74HC132), generating a brief reset pulse (/250HZ) which is then inverted by another U8 gate, then stretched via the C8/R26 network, thus creating the ST250 signal which both serves as a U14 counter reset and, after a diode to turn it open-collector/open-drain, as the main /IRQ generator for the 65C02, without interfering other uses of this signal (nanoLink, cartridge etc).
Check the interrupt troubleshooting guide for extra information about this.
Note
v2 issue has a somewhat faster system clock (1.75 MHz). Thus, VA0 is more like 875 KHz, so the division factor for the 74HC4040 becomes 3500 instead of 3072 for the specified 250 Hz. Being a much less nicer number in the binary sense, an 8-input NAND gate (74HC30) is used for generating /250HZ and half of U29 (74HC139) is configured as an inverter for this pulse, then stretched in a similar way, although using one buffer from U32 (74HC245) instead of a Schmitt-trigger gate.
Note that the TURBO option does not affect the interrupt speed, as the counter is fed from VA0, which must run always at the same speed.
Note
The simplified, Compact version of Durango (under development), generates ST250 thru a flange detector from VA11 which, despite its somewhat irregular rhythm, does in the long term run at around the specified 250 Hz, although the 4 ms spacing is no longer guaranteed. This way, U14 is eliminated altogether.
MUX
Base I/O
Extra features
Interface
